1. Field of the Invention
The present invention relates generally to a clock distribution network, and in particular, to a computer implemented method for managing the placement of local clock buffers. More particularly, the present invention relates to a computer implemented method, system, and computer usable program code for managing latch clustering with proximity to local clock buffers.
2. Description of the Related Art
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of an integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have been partially or fully automated. Several different programming languages have been created for electronic design automation (EDA) including Verilog (Verilog is a trademark of the Gateway Design Automation Corporation in the United States), VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an integrated circuit (IC) device, and translates this high level design language description into netlists of various levels of abstraction.
While current placement techniques provide adequate placement of cells with regard to their data interconnections, there is an additional challenge for the designer in constructing a clock network for the cells. In a synchronous digital system, a clock signal is used to define a time reference for the movement of data within the system. The clock distribution network, or clock tree, distributes the clock signal from a common point to all the elements that need the clock signal.
The difference in the arrival time of a common clock signal at various locations in the physical layout of an integrated circuit design is called clock skew. The variation in the clock period at various locations in the physical layout of an integrated circuit design is called jitter. Both clock skew and clock jitter may result in decreased performance capability in terms of maximum operating frequency and in circuit malfunction from setup and hold time violations.
Constructing a clock network for the cells is becoming more difficult with the latest technologies like low-power 65-nanometer integrated circuits. Low power circuits such as those around 20 Watts or less for microprocessor chips are becoming more prevalent due to power consumption problems. In particular, power dissipation has become a limiting factor for the yield of high-performance circuit designs with deep submicron technology. Clock nets can contribute up to 50 percent of the total active power in multi-GHz designs. Low power designs are also preferable since they exhibit less power supply noise and provide better tolerance with regard to manufacturing variations.
There are several techniques for minimizing power while still achieving timing objectives for high performance, low power systems. One method involves the use of local clock buffers (LCBs) to distribute the clock signals. A typical clock control system has a clock generation circuit that generates a master clock signal which is fed to a clock distribution network that renders synchronized global clock signals at the LCBs. Each LCB adjusts the global clock duty cycle and edges to meet the requirements of respective circuit elements, e.g., local logic circuits or latches. Typically, a proximity constraint or distance from a latch to a LCB is required to ensure the clock skew and clock jitter are within desired tolerances.
Because the clock network is one of the largest power consumers among all of the interconnected components, controlling the capacitive load of the LCBs may be beneficial. One approach for reducing the capacitive load is latch clustering, or clusters of latches placed near the respective LCB of their clock domain. Latch clustering combined with LCBs can significantly reduce the total clock wire capacitance which in turn reduces overall clock power consumption. Since most of the latches are placed close to an LCB, clock skew is also reduced which helps improve the timing of the circuit.
Conventional placement begins with an initial placement of the latches based on a layout for the circuit. The layout can be provided by an EDA tool that places the latches in an optimal placement for each logic cells. The latches are grouped into a given latch cluster based on locality and clock domain. The LCB for a given clock domain is located at the center of the latch cluster and the latches are pulled to the LCB. However, as the latches are pulled to the LCB, the latches become displace away from their optimal placement and timing degradation can occur. An improved placement method that could balance between timing degradation and latch to LCB timing constraints would therefore be desirable.